| 1. | Synchronous construction reduces the delay time of a counter to the delay of: ? | |
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all flip-flops and gates
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all flip-flops and gates after a 3 count
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a single gate
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a single flip-flop and a gate
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Report Question| 2. | A BCD counter is a ________ ? | |
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binary counter
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full-modulus counter
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decade counter
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divide-by-10 counter
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| 3. | How many different states does a 3-bit asynchronous counter have ? | |
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2
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4
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8
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16
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| 4. | An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required ? | |
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None
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One
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Two
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Fifteen
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| 5. | A 4-bit counter has a maximum modulus of ________ ? | |
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2
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6
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8
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16
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| 6. | Which of the following is a type of shift register counter ? | |
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Decade
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Binary
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Ring
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BCD
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| 7. | To operate correctly, starting a ring shift counter requires: ? | |
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clearing all the flip-flops
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presetting one flip-flop and clearing all others
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clearing one flip-flop and presetting all others
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presetting all the flip-flops
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| 8. | How many flip-flops are required to construct a decade counter ? | |
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10
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8
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5
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4
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| 9. | A MOD-16 ripple counter is holding the count 1001. What will the count be after 31 clock pulses ? | |
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1000
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1010
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1011
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1101
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| 10. | The primary purpose of a three-state buffer is usually: ? | |
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to provide isolation between the input device and the data bus
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to provide the sink or source current required by any device connected to its output without loading down the output device
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temporary data storage
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to control data flow
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