| 1. | What is the resolution of a digital-to-analog converter (DAC) ? | |
|
It is the comparison between the actual output of the converter and its expected output
|
||
|
It is the deviation between the ideal straight-line output and the actual output of the converter
|
||
|
It is the smallest analog output change that can occur as a result of an increment in the digital input
|
||
|
It is its ability to resolve between forward and reverse steps when sequenced over its entire range
|
||
View Answer
Discuss in Forum
Report Question| 2. | The difference between analog voltage represented by two adjacent digital codes, or the analog step size, is the: ? | |
|
quantization
|
||
|
accuracy
|
||
|
resolution
|
||
|
monotonicity
|
||
| 3. | The primary disadvantage of the flash analog-to digital converter (ADC) is that: ? | |
|
it requires the input voltage to be applied to the inputs simultaneously
|
||
|
a long conversion time is required
|
||
|
a large number of output lines is required to simultaneously decode the input voltage
|
||
|
a large number of comparators is required to represent a reasonable sized binary number
|
||
| 4. | In a flash analog-to-digital converter, the output of each comparator is connected to an input of a: ? | |
|
decoder
|
||
|
priority encoder
|
||
|
multiplexer
|
||
|
demultiplexer
|
||
| 5. | What is the disadvantage to using a counter-ramp type ADC ? | |
|
complex circuit
|
||
|
high cost
|
||
|
very slow
|
||
|
none
|
||
| 6. | The number of comparators in a parallel conversion type 8-bit analog to digital converter is ? | |
|
8
|
||
|
16
|
||
|
255
|
||
|
256
|
||
| 7. | A simultaneous A/D converter is also known as a(n) ________ A/D converter ? | |
|
flash
|
||
|
synchronous
|
||
|
comparator
|
||
|
asynchronous
|
||
| 8. | The main advantage of the successive-approximation A/D converter over the counter ramp A/D converter is its: ? | |
|
more complex circuitry
|
||
|
less complex circuitry
|
||
|
longer conversion time
|
||
|
shorter conversion time
|
||
| 9. | Sample-and-hold circuits in analog-to digital converters (ADCs) are designed to: ? | |
|
sample and hold the output of the binary counter during the conversion process
|
||
|
stabilize the comparator's threshold voltage during the conversion process
|
||
|
stabilize the input analog signal during the conversion process
|
||
|
sample and hold the D/A converter staircase waveform during the conversion process
|
||
| 10. | What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to a binary-weighted digital-to-analog DAC converter ? | |
|
It only uses two different resistor values
|
||
|
It has fewer parts for the same number of inputs
|
||
|
Its operation is much easier to analyze
|
||
|
The virtual ground is eliminated and the circuit is therefore easier to understand and troubleshoot
|
||