| 1. | The characteristic equation of an SR flip-flop is given by ? | |
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Qn+1 = S+RQn
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Qn+1=RQ’n+S’Qn
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Qn+1 = S’+RQn
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Qn+1=S+R’Q
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Report Question| 2. | A J-K flip-flop can be made from an S-R flip-flop by using two additional ? | |
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NAND gates
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OR gates
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NOT gates
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NOR gates
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| 3. | The output Qn of a J-K flip-flop is zero. It changes to 1 when a clock pulse is applied. The input Jn, and Kn, are respectively ? | |
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1 and X
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0 and X
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X and 0
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X and 1
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| 4. | If both inputs of S-R NAND latch are low, the output will be ? | |
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unpredictable
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toggle
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reset
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remain same
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| 5. | An R-S latch is a ? | |
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combinational circuit
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synchronous circuit
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one bit memory element
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one clock delay element
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| 6. | Which of the following flip flop is used as a latch ? | |
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J-K flip-flop
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RS flip-flop
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T flip-flop
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D flip-flop
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| 7. | Which one of the following equations satisfies the JK flip-flop truth table ? | |
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Qn+1 = JnQ’n+K’nQn
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Qn+1 = J’nQ’n+K’nQn
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Qn+1 = JnQn + KnQn
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Qn+1 = J’nQ’n + K’nQ’n
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| 8. | When J = K = 1 in a J-K flip-flop, the output ? | |
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is set
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is reset
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goes to tristate
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toggles
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| 9. | The characteristic equation for the next state (Qn+1) of a J-K flop is ? | |
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Qn+1 = JQn+ KQ’n
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Qn+1 = J’Q’n+ K’Q’n
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Qn+1 = JQ’n+ K’Qn
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Qn+1 = JQn + KQn
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| 10. | The both 1 state is forbidden for ? | |
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J-K flip-flop
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D flip-flop
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R-S flip-flop
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T flip-flop
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