6 MHz

10 MHz

3 MHz

12MHz

Accumulator logic execution

Arithmetic logic execution

Address latch enable

All enable

8085 is ready but peripheral device is not ready

Both 8085 and peripheral device are not ready

8085 is not ready but peripheral device is ready

Both 8085 and peripheral device are ready

Maskable, highest priority and software interrupt

Nonmaskable, highest priority and hardware interrupt

Nonmaskable, highest priority and software interrupt

Maskable, lowest priority and hardware interrupt

I/O devices have 8 bit address

I/O devices are accessed using IN and OUT instruction

There can be maximum 256 input and 256 output devices

Arithmetic and logic operations can be directly performed with I/O data

non-maskable: maskable

non-maskable: non-maskable

Maskable: maskable

Maskable: non-maskable

Stop execution of instructions

Acknowledges interrupt and branches off subroutine

Acknowledges interrupt and continues interrupt

Acknowledges interrupt and waits for the next instruction from the interrupting device

All the register & counters are being reset and in addition this signal can be used to reset external support chip

Processing can begin when this signal goes high

All the register & counters are being reset

All the register of the CPU are being reset

Data transfer instruction

Logical instruction

Branching instruction

Arithmetic instruction

8 bit nmos

8 bit cmos

8 bit Pmos

8 bit hmos